1. Field of the Invention
The present invention relates to a memory interface circuit comprising a function for refreshing memory. The present invention can be applied to a memory interface circuit, which is used, for example, in an ordinary DRAM (Dynamic Random Access Memory), and a synchronous DRAM.
2. Description of Related Art
As is commonly known, a DRAM stores binary data in accordance with whether or not a charge is stored on a capacitor in each memory cell. For this reason, an operation, which replenishes the charge to each memory cell capacitor, is necessary to prevent a memory value from being destroyed by capacitor leakage current. This operation is called “refresh.”
In a DRAM, refresh must be performed cyclically to ensure the prevention of memory data destruction. Therefore, in an ordinary DRAM, the execution of a refresh operation takes priority over a read/write operation. That is, a DRAM will make a read/write access wait, and accept a refresh access first.
However, if read/write access is made to wait every refresh cycle, the time required for a DRAM read operation and write operation will substantially increase. For this reason, for a highspeed system, there are cases in which the performance of the entire system deteriorates because read/write operations are slow. Further, depending on the system, there are also cases in which malfunctions occur because of a slow response to a read/write request.